It is known in the art to maintain state machines, typically consisting of state tables, defining the states of elements associated with a system. An example of such a state machine is the collection of state tables forming Postal State Tables (PSTs) stored in flash memory and utilized in postal printing devices. The PSTs maintain data related to the status of purchased postal indicia.
As noted, such state tables are typically stored in flash memory. It is an unfortunate attribute of flash memory that such memory possesses a relatively limited number of erase cycles. For example, flash memory internal to a processor may only allow one hundred erase cycles. The actual number of erase cycles that may be performed before experiencing a significant degradation in the operation of the memory varies. However, when such degradation does occur, the result is an increase in the amount of time to write to the flash memory and to retrieve data from the flash memory. As a result, it is desirable to minimize the number of erase cycles.
In a typical erase cycle, each bit in the flash memory device is set to logical “1”. In order to limit the number of erases performed on a flash memory, it is noted that any bit can be transitioned from a one to a zero between erase cycles (or from a zero to a one depending on the flash part). This fact allows multiple writes to occur in a flash memory device between erases. It is therefore preferable to manipulate data stored on a flash memory in a manner requiring only the transition of bits from one to zero. By so doing, one decreases the frequency with which the flash memory requires erasing.
In addition, it is preferable to employ an algorithm to efficiently clean the non-volatile memory (NVM), such as flash memory, such that erases occur only when required. When an erase cycle is needed, it is further preferable to engage in erasing flash memory in such a way that the entire flash memory experiences a generally uniform application of memory erasing.